Efficient Majority Voting in Digital Hardware

In recent years, machine learning methods became increasingly important for a manifold number of applications. However, they often suffer from high computational requirements impairing their efficient use in real-time systems, even when employing dedicated hardware accelerators. Ensemble are especially suitable acceleration since can be constructed individual learners low complexity and thus offer large parallelization potential. For classification, the outputs these typically combined by majority voting, which represents bottleneck accelerator ensemble inference. this brief, we present novel architecture that allows obtaining decision clock cycles is logarithmic inputs. We show, example application handwritten digit recognition random forest processing engine implemented on an FPGA classification more than seven million images per second, resulting speed-up factor 29 compared to fastest state-of-the-art implementation considered.